搜索资源列表
rom_des.zip
- DES 加密算法的VHDL和VERILOG 源程序及其TESTBENCH。
ADPLL
- verilog ADPLL file with testbench.v
usb1_funct
- usb1.1的verilog源代码。以及其测试仿真文件,现在很难找其测试文件既testbench-usb1.1 verilog the source code. Simulation and test document, and now it is very difficult to find the paper test testbench
16bit_booth_multiplier_STG
- verilog程序,实现两个16bit数乘法,采用booth算法,基于状态机实现,分层次为datapath和controller两个子模块,testBench测试通过-verilog procedures, two 16bit multiplication, the algorithm used booth. Based on the state machine achieved at different levels for datapath controller and two sub-mo
hdb3_verilog
- modelsim工程,用verilog实现的HDB3编码,以及测试程序testbench-modelsim works with verilog realized HDB3 coding, and testing procedures testbench
oc8051
- 8051的verilog实现,内附testbench,c语言调试程序-8051 verilog achieve, enclosing testbench, c language debugging procedures
FIFO_v
- FIFO的verilog实现,内附testbench和文档说明-FIFO verilog achieve, enclosing testbench and documentation shows
s_fifo
- 一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench
dac
- DAC converter design with Verilog code and testbench
crc16_ccitt
- crc_table.c is for reset seed( 0000 ) crc_table_1.c is for reset seed( ffff) CRC16_D8_m.v is a verilog module of byte paralle crc. CRC16_D8_m_tb.v is the testbench file of above module.
DCT
- altera fpga verilog 设计的基于查找表的DCT程序及zigzag扫描程序,已经过matlab 和modelsim 验证,文件中包含TESTBENCH ,直接可用
flash接口控制_verilog
- flash接口控制器的VHDL以及verilog源代码和Testbench程序-flash interface controller VHDL and Verilog source code and procedures Testbench
Chapter10
- 第十章的代码。 本书通过100多个模块实例,详细地讲解了Verilog HDL程序设计语言,全书共分13章,内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等,实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相
spi slave程序
- spi slave的verilog程序,有测试平台testbench程序,实现fpga作为salve的功能(spi slave verilog program)
uart_rx
- Verilog实现的RS232发送和接收程序,有完成的verilog代码,testbench等。(UART send and receive verilog code, including verilog source code, testbench etc.)
ethernet_ip_verilog
- 以太网的ip,用verilog写的,包含testbench,用于FPGA以太网设计参考
W25Q80NE verilog Model
- SPI FLASH官方仿真模型方便modelsim testbench调试仿真(Official simulation model facilitates debugging and simulation)
SPI接口Verilog实现
- 里面有主机发送模块和从机接收模块。主机发送32位16进制数(一位一位发送),工作在模式0。压缩文件内代码可直接运行,另附上testbench文件可以进行modelsim仿真。此代码根据论坛里一位大哥的代码改编,后来找不到是谁了。。。使用状态机编写主机的发送模块,由于项目仅仅需要主机发送所以从机的接收模块没有写成32位的,但是代码风格清晰,可以直接修改,复写率极高且非常好理解!
Verilog实现IIC通信协议
- Verilog实现IIC通信协议,里面有IIC master和slave的源码,以及testbench仿真的代码